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r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 rev. 0.11 2013.01.15 description the r1q # a7236 is a 2,097,152-word by 36-bit and the r1q # a7218 is a 4,194,304-word by 18-bit synchronous quad data rate static ram fabricated with advanced cmos technology using full cmos six-transistor memory cell. it integrates unique synchronous peripheral circuitry and a burst counter. all input registers are controlled by an input clock pair (k and /k) and are latched on the positive edge of k and /k. these products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. these products are packaged in 165-pin plastic fbga package. # = a: read latency =2.5, w/o odt # = g: read latency =2.0, w/o odt # = d: read latency =2.5, w/ odt # = k: read latency =2.0, w/ odt hint=00000.0000 . 0000 . 1100 . 1100 -- - 00000.0000.0000.0000.0000--- 00000.0000.0000.0000.000 0--- qdrii+_rl20 features ? power supply ? 1.8 v for core (v dd ), 1.4 v to v dd for i/o (v ddq ) ? clock ? fast clock cycle time for high bandwidth ? two input clocks (k and /k) for precise ddr timing at clock rising edges only ? two output echo clocks (cq and /cq) simplify data capture in high-speed systems ? clock-stop capability with s restart ? i/o ? separate independent read and write data ports with concurrent transactions ? 100% bus utilization ddr read and write operation ? hstl i/o ? user programmable output impedance ? dll/pll circuitry for wide output data valid window and future frequency scaling ? data valid pin (qvld) to indicate valid data on the output ? function ? four-tick burst for reduced address frequency ? internally self-timed write control ? simple control logic for easy depth expansion ? jtag 1149.1 compatible test access port ? package ? 165 fbga package (13 x 15 x 1.4 mm) r1qga7236abb / r1qga7218abb r1qka7236abb / r1qka7218abb 72-mbit qdr?ii+ sram 4-word burst notes: 1. qdr rams and quad data rate rams comprise a new family of products developed by cypress semiconductor, idt, samsung, and renesas electronics corp. (qdr co-development team) 2. the specifications of this device are subject to change without notice. please contact your nearest renesas electronics sales office regarding specifications. 3. refer to " http://www.renesas.com/products/memory/fast_sram/qdr_sram/index.jsp " for the latest and detailed information. 4. descriptions about x9 parts in this datasheet are just for reference. r10ds0172ej0011 r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 part number definition common part number definition table column no. 0 1 2 3 4 5 6 7 8 9 10 11 - 12 13 14 15 16 example r1qga7218abb - 25rb0 the above part number is just example for 72m qdrii+ b4 x18 400mhz, 13x15mm pkg, pb-free part. no. - comments no. - comments no. - comments 0-1 r1 renesas memory prefix 4 a vdd = 1.8 v 60 frequency = 167mhz q2 qd r ii b 2 [*1] (l15) [*2] 36 density = 36mb 50 frequency = 200mhz q3 qdr ii b4 (l15) 72 density = 72mb 40 frequency = 250mhz q4 ddr ii b2 (l15) 44 density = 144mb 36 frequency = 275mhz q5 ddr ii b4 (l15) 88 density = 288mb 33 frequency = 300mhz q6 ddr ii b2 sio [*3] (l15) 09 data width = 9bit 30 frequency = 333mhz qa qd r ii+ b 4 l 25 [*2] 18 data width = 18bit 27 frequency = 375mhz qb ddr ii+ b2 l25 36 data width = 36bit 25 frequency = 400mhz qc ddr ii+ b4 l25 r 1st generation 22 frequency = 450mhz qd qdr ii+ b4 l25 w/odt [*4] a 2nd generation 20 frequency = 500mhz qe ddr ii+ b2 l25 w/odt b 3rd generation 19 frequency = 533mhz qf ddr ii+ b4 l25 w/odt c 4th generation 18 frequency = 550mhz qg qdr ii+ b4 l20 d 5th generation qh ddr ii+ b2 l20 e 6th generation qj ddr ii+ b4 l20 f 7th generation qk qdr ii+ b4 l20 w/odt bg pkg= bga 15x17 mm ql ddr ii+ b2 l20 w/odt bb pkg= bga 13x15 mm a pb - and tray qm ddr ii+ b4 l20 w/odt b pb-free and tray qn qdr ii+ b2 l20 tpb - and tape&reel qp qdr ii+ b2 l20 w/odt s pb-free and tape&reel note1: [*1] b=burst length (b2: burst length=2, b4: burst length=4) [*2] l=read latency (l15: read latency = 1.5 cycle, l20: 2.0 cycle, l25: 2.5 cycle) [*3] sio=separate i/o [*4] odt=on die termination note2: package marking name pb - parts: marking name = part number(0-14) pb-free parts: marking name = part number(0-14) + "pb-f" (example) r1qaa4436rbg-20r pb-f ----- pb - parts (example) r1qaa4436rbg-20r pb-f ----- pb-free parts note3: pb -free : rohs compliance level = 5/6 pb-free: rohs compliance level = 6/6 note4: r1q*a series support both "commercial" and "industrial" temperatures by "industrial" temperature parts. r commercial temp. ta range = 0 to 70 12-13 14 2-3 5-6 7-8 9 - 16 0 to 9, a to z or none renesas internal use 10-11 --- - industrial temp. ta range = -40 to 85 i 15 r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 hins=11111.1111 .1111.1111.1111-- - 00000.0000.0000.0000.0000--- 00000.0000.0000.0000.0000---072m notes: 1. " v " represents the package size . if " v " = " g " then size is 15 x 17 mm, and if " v " = " b " then 13 x 15 mm. 2. " yy " represents the speed bin . "r1qaa7236abb- 20 " can operate at 500 mhz(max) of frequency, for example. 3. the part which is not listed above is not supported, as of the day when this datasheet was issued, in spite of the existence of the part number or datasheet. 533 500 450 400 375 333 333 300 250 200 1.875 2.00 2.22 2.50 2.66 3.00 3.00 3.30 4.00 5.00 yy -19-20-22-25-27-30-30-33-40-50 1 x 9 r1q 2 a72 09 a b v - yy -40 -50 2x18r1q2a7218ab v - yy 3x36r1q2a7236ab v - yy 5x18r1q3a7218ab v - yy 6x36r1q3a7236ab v - yy 8x18r1q4a7218ab v - yy 9x36r1q4a7236ab v - yy 11 x18 r1q 5 a72 18 a b v - yy 12 x36 r1q 5 a72 36 a b v - yy 14 x18 r1q 6 a72 18 a b v - yy 15 x36 r1q 6 a72 36 a b v - yy 17 x18 r1q a a72 18 a b v - yy 18 x36 r1q a a72 36 a b v - yy 20 x18 r1q b a72 18 a b v - yy 21 x36 r1q b a72 36 a b v - yy 23 x18 r1q c a72 18 a b v - yy 24 x36 r1q c a72 36 a b v - yy 26 x18 r1q d a72 18 a b v - yy 27 x36 r1q d a72 36 a b v - yy 29 x18 r1q e a72 18 a b v - yy 30 x36 r1q e a72 36 a b v - yy 32 x18 r1q f a72 18 a b v - yy 33 x36 r1q f a72 36 a b v - yy 35 x18 r1q g a72 18 a b v - yy 36 x36 r1q g a72 36 a b v - yy 38 x18 r1q h a72 18 a b v - yy 39 x36 r1q h a72 36 a b v - yy 41 x18 r1q j a72 18 a b v - yy 42 x36 r1q j a72 36 a b v - yy 44 x18 r1q k a72 18 a b v - yy 45 x36 r1q k a72 36 a b v - yy 47 x18 r1q l a72 18 a b v - yy 48 x36 r1q l a72 36 a b v - yy 50 x18 r1q m a72 18 a b v - yy 51 x36 r1q m a72 36 a b v - yy -30 -30 qdr ii+ / ddr ii+ qdr ii / ddr ii -30 -30 -40 -50 -33 frequency (max) (mhz) cycle time (min) (ns) no yes no odt part number -19 -19 -19 -19 -22 -22 -22 -22 b2 -19 -19 1.5 no 2.5 2.5 b4 b2 b2 yes b4 qdrii ddrii sio b2 b2 ddrii+ ddrii b4 qdrii+ qdrii+ b4 2.0 ddrii+ b2 b4 2.0 b4 ddrii+ qdrii+ b4 ddrii+ b2 b4 qdrii+ b4 no product type burst length latency (cycle) b4 organi- zation -20 -20 -20 -20 -20 -20 -40 -40 -40 -40 -22 -22 -25 -25 -25 -33 -25 -33 -33 -25 -25 72m qdr/ddr sram (r1q*a72 series) lineup - renesas supports or plans to support the parts listed below. r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 r1q3a7218 (top) / r1qa(g)a7218 (mid) / r1qd(k)a7218 (bottom) 1234567891011 a /cq nc sa /w /bw1 /k nc /r sa sa cq b nc q9 d9 sa nc k /bw0 sa nc nc q8 cncncd10v ss sa nc sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 encncq11v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h/doffv ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq jncncd14v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 mncncd16v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa c qvld qvld sa sa nc d0 q0 rtdotcksasasa /c nc odt sa sa sa tms tdi (top view) notes: 1. address expansion order for future higher density srams: 10a : 2a : 7a : 5b. 2. nc pins can be left floating or connected to 0v : v ddq . r1q3a7236 (top) / r1qa(g)a7236 (mid) / r1qd(k)a7236 (bottom) 1234567891011 a /cq nc sa /w /bw2 /k /bw1 /r sa nc cq b q27 q18 d18 sa /bw3 k /bw0 sa d17 q17 q8 c d27 q28 d19 v ss sa nc sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h/doffv ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d35 q26 sa sa c qvld qvld sa sa q9 d0 q0 rtdotcksasasa /c nc odt sa sa sa tms tdi (top view) notes: 1. address expansion order for future higher density srams: 10a : 2a : 7a : 5b. 2. nc pins can be left floating or connected to 0v : v ddq . pin arrangement 72--- top 8 r1q3a7236 mid 8 r1qa(g)a7236 bottom 8 r1qd(k)a7236 r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 r1q3a7209 (top) / r1qa(g)a7209 (mid) / r1qd(k)a7209 (bottom) 1234567891011 a /cq sa sa /w nc /k nc /r sa sa cq b ncncncsanc k /bwsancncq4 c ncncncv ss sa nc sa v ss nc nc d4 dncd5ncv ss v ss v ss v ss v ss nc nc nc encncq5v ddq v ss v ss v ss v ddq nc d3 q3 f ncncncv ddq v dd v ss v dd v ddq nc nc nc gncd6q6v ddq v dd v ss v dd v ddq nc nc nc h/doffv ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j ncncncv ddq v dd v ss v dd v ddq nc q2 d2 k ncncncv ddq v dd v ss v dd v ddq nc nc nc lncq7d7v ddq v ss v ss v ss v ddq nc nc q1 m ncncncv ss v ss v ss v ss v ss nc nc d1 nncd8ncv ss sa sa sa v ss nc nc nc pncncq8sasa c qvld qvld sa sa nc d0 q0 rtdotcksasasa /c nc odt sa sa sa tms tdi (top view) notes: 1. address expansion order for future higher density srams: 10a : 2a : 7a : 5b. 2. nc pins can be left floating or connected to 0v : v ddq . pin arrangement 72--- just reference r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 pin descriptions name i/o type descriptions notes sa input synchronous address inputs: these inputs are registered and must meet the setup and hold times around the rising edge of k. all transactions operate on a burst-of-four words (two clock periods of bus activity). these inputs are ignored when device is deselected. /r input synchronous read: when low, this input causes the address inputs to be registered and a read cycle to be initiated. this input must meet setup and hold times around the rising edge of k, and is ignored on the subsequent rising edge of k. /w input synchronous write: when low, this input causes the address inputs to be registered and a write cycle to be initiated. this input must meet setup and hold times around the rising edge of k, and is ignored on the subsequent rising edge of k. /bw x input synchronous byte writes: when low, these inputs cause their respective byte to be registered and written during write cycles. these signals are sampled on the same edge as the corresponding data and must meet setup and hold times around the rising edges of k and /k for each of the two rising edges comprising the write cycle. see byte write truth table for signal to data relationship. k, /k input input clock: this input clock pair registers address and control inputs on the rising edge of k, and registers data on the rising edge of k and the rising edge of /k. /k is ideally 180 degrees out of phase with k. all synchronous inputs must meet setup and hold times around the clock rising edges. these balls cannot remain v ref level. c, /c (ii only) input output clock: this clock pair provides a user-controlled means of tuning device output data. the rising edge of /c is used as the output timing reference for the first and third output data. the rising edge of c is used as the output timing reference for second and fourth output data. ideally, /c is 180 degrees out of phase with c. c and /c may be tied high to force the use of k and /k as the output reference clocks instead of having to provide c and /c clocks. if tied high, c and /c must remain high and not to be toggled during device operation. these balls cannot remain v ref level. 1 /doff input dll/pll disable: when low, this input causes the dll/pll to be bypassed for stable, low frequency operation. tms tdi input ieee1149.1 test inputs: 1.8 v i/o levels. these balls may be left not connected if the jtag function is not used in the circuit. tck input ieee1149.1 clock input: 1.8 v i/o levels. this ball must be tied to v ss if the jtag function is not used in the circuit. notes: 1. r1q2, r1q3, r1q4, r1q5, r1q6 series have c and /c pins. r1qa, r1qb, r1qc, r1qd, r1qe, r1qf, r1qg, r1qh, r1qj, r1qk, r1ql, r1qm, r1qn, r1qp series do not have c, /c pins. in the series, k and /k are used as the output reference clocks instead of c and /c. therefore, hereafter, c and /c represent k and /k in this document. hins=11000.1100.1100.1100.1100 --- 11000.1100.1100.1100.1100 --- 11000.1100.1100.1100.1100--- qdr r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 name i/o type descriptions notes zq input output impedance matching input: this input is used to tune the device outputs to the system data bus impedance. q and cq output impedance are set to 0.2 rq, where rq is a resistor from this ball to ground. this ball can be connected directly to v ddq , which enables the minimum impedance mode. this ball cannot be connected directly to v ss or left unconnected. in odt (on die termination) enable devices, the odt termination values tracks the value of rq. the odt range is selected by odt control input. odt (ii+ only) input odt control: when low ; [option 1] low range mode is selected. the impedance range is between 52 and 105 (thevenin equivalent), which follows 0.3 rq for 175 ? rq ? 350 . [option 2] odt is disabled. when high ; high range mode is selected. the impedance range is between 105 and 150 (thevenin equivalent), which follows 0.6 rq for 175 ? rq ? 250 . when floating ; [option 1] high range mode is selected. [option 2] odt is disabled. 1 d 0 to d n input synchronous data inputs: input data must meet setup and hold times around the rising edges of k and /k during write operations. see pin arrangement figures for ball site location of individual signals. the 9 device uses d0 ~ d8. d9 ~ d35 should be treated as nc pin. the 18 device uses d0 ~ d17. d18 ~ d35 should be treated as nc pin. the 36 device uses d0 ~ d35. cq, /cq output synchronous echo clock outputs: the edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. these signals run freely and do not stop when q tri- states. tdo output ieee 1149.1 test output: 1.8 v i/o level. q 0 to q n output synchronous data outputs: output data is synchronized to the respective c and /c, or to the respective k and /k if c and /c are tied high. this bus operates in response to /r commands. see pin arrangement figures for ball site location of individual signals. the 9 device uses q0 ~ q8. q9 ~ q35 should be treated as nc pin. the 18 device uses q0 ~ q17. q18 ~ q35 should be treated as nc pin. the 36 device uses q0 ~ q35. qvld (ii+ only) output valid output indicator: the q valid indicates valid output data. qvld is edge aligned with cq and /cq. v dd supply power supply: 1.8 v nominal. see dc characteristics and operating conditions for range. 2 v ddq supply power supply: isolated output buffer supply. nominally 1.5 v. see dc characteristics and operating conditions for range. 2 v ss supply power supply: ground. 2 v ref ? hstl input reference voltage: nominally v ddq /2, but may be adjusted to improve system noise margin. provides a reference voltage for the hstl input buffers. nc ? no connect: these pins can be left floating or connected to 0v : v ddq . notes: 1. renesas status: option 1 = available, option 2 = possible. 2. all power supply and ground balls must be connected for proper operation of the device. --- r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 72--- block diagram (r1qxa7236 / r1qxa7218 / r1qxa7209, x=3,a,d,g,k) address /r /w k /k /w /bwx d (data in) /r k /k 72 /36 /18 144 /72 /36 19/20/21 36/18/9 36/18/9 q (data out) 19/20/21 k c,/c or k,/k zq 2 cq /cq 72 /36 /18 address registry and logic data registry and logic memory array write register output register output select output buffer write driver sense amp mux mux 72 /36 /18 72 /36 /18 4/2/1 notes 1. c and /c pins do not exist in ii+ series parts. c or k r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 hins= 11111.1111 .1111.1111.1111-- - 11111.1111 .1111.1111.1111 ---00000.0000.0000.0000.0000 --- 72m_36m status power up & unstable stage nop & set-up stage normal operation v dd set-up cycle v ddq v ref /doff 2. double clock mode k, /k fix high (=vddq) c, /c status power up & unstable stage nop & set-up stage normal operation v dd set-up cycle v ddq v ref /doff 1. single clock mode (c and /c pins fixed high) k, /k fix high (=vddq) general description power-up and initialization sequence -v dd must be stable before k, /k clocks are applied. - recommended voltage application sequence : v ss : v dd : v ddq & v ref : v in . (0 v to v dd , v ddq < 200 ms) - apply v ref after v ddq or at the same time as v ddq . - then execute either one of the following three sequences. 1. single clock mode (c and /c tied high) - drive /doff high (/doff can be tied high from the start). - then provide stable clocks (k, /k) for at least 1024 cycles (ii series) or 20 us (ii+ series). these meet the qdr common specification of 20 us. when the operating frequency is less than 180 mhz, 2048 cycles are required (ii series). 2. double clock mode (c and /c control outputs) ( ii series only ) - drive /doff high (/doff can be tied high from the start) - then provide stable clocks (k, /k , c, /c) for at least 1024 cycles (ii series). this meets the qdr common specification of 20 us. when the operating frequency is less than 180 mhz, 2048 cycles are required (ii series). 3. dll/pll off mode (/doff tied low) - in the "nop and setup stage", provide stable clocks (k, /k) for at least 1024 cycles (ii series) or 20 us (ii+ series). these meet the qdr common specification of 20 us. r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 common dll/pll constraints 1. dll/pll uses k clock as its synchronizing input. the input should have low phase jitter which is specified as tkc var. 2. the lower end of the frequency at which the dll/pll can operate is 120 mhz. (please refer to ac characteristics table for detail.) 3. when the operating frequency is changed or /doff level is changed, setup cycles are required again. programmable output impedance 1. output buffer impedance can be programmed by terminating the zq ball to v ss through a precision resistor (rq). the value of rq is five times the output impedance desired. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is 250 typical. the total external capacitance of zq ball must be less than 7.5 pf. r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 iip qvld (valid data indicator) (r1qa, r1qb, r1qc, r1qd, r1qe, r1qf, r1qg, r1qh, r1qj, r1qk, r1ql, r1qm r1qn, r1qp series) 1. qvld is provided on the qdr-ii+ and ddr-ii+ to simplify data capture on high speed systems. the q valid indicates valid output data. qvld is activated half cycle before the read data for the receiver to be ready for capturing the data. qvld is inactivated half cycle before the read finish for the receiver to stop capturing the data. qvld is edge aligned with cq and /cq. odt range odt control pin thevenin equivalent resistance (r thev ) unit notes option 1 option 2 - 6 low 0.3 rq (odt disable) 1, 4 high 0.6 rq 0.6 rq 2, 5 floating 0.6 rq (odt disable) 3 notes: 1. allowable range of rq for option 1 to guarantee impedance matching a tolerance of 20 % is 175 ? rq ? 350 . 2. allowable range of rq to guarantee impedance matching a tolerance of 20 % is 175 ? rq ? 250 . 3. allowable range of rq for option 1 to guarantee impedance matching a tolerance of 20 % is 175 ? rq ? 250 . 4. at option 1, odt control pin is connected to v ddq through 3.5 k . therefore it is recommended to connect it to v ss through less than 100 to make it low. 5. at option 2, odt control pin is connected to v ss through 3.5 k . therefore it is recommended to connect it to v ddq through less than 100 to make it high. 6. renesas status: option 1 = available, option 2 = possible. if you need devices with option 2, please contact renesas sales office. odt (on die termination) (r1qd, r1qe, r1qf, r1qk, r1ql, r1qm, r1qp series) 1. to reduce reflection which produces noise and lowers signal quality, the signals should be terminated, especially at high frequency. renesas offers odt on the input signals to qdr-ii+ and ddr-ii+ family of devices. (see the odt pin table) 2. in odt enable devices, the odt termination values tracks the value of rq. the odt range is selected by odt control input. (see the odt range table) 3. in ddr-ii+ devices having common i/o bus, odt is automatically enabled when the device inputs data and disabled when the device outputs data. 4. there is no difference in ac timing characte ristics between the srams with odt and srams without odt. 5. there is no increase in the i dd of srams with odt, however, there is an increase in the i ddq (current consumption from the i/o voltage supply) with odt. r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 iip thevenin termination output buffer sram with odt 2 r thev 2 r thev v ddq other lsi input buffer v ss zq v ss rq odt pin (r1qd, r1qe, r1qf, r1qk, r1ql, r1qm, r1qp series) pin name odt on/off timing notes option 1 option 2 3 odt pin = high odt pin = low or floating d 0 ~d n in separate i/o devices always on always off 1 dq 0 ~dq n in common i/o devices off: first read command + read latency - 0.5 cycle on: last read command + read latency + bl/2 cycle + 0.5 cycle (see below timing chart) always off 2 /bw x always on always off k, /k always on always off notes: 1. separate i/o devices are r1qd, r1qk, r1qp series. 2. common i/o devices are r1qe, r1qf, r1ql, r1qm series. 3. renesas status: option 1 = available, option 2 = possible. if you need devices with option 2, please contact renesas sales office. r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 iip nop command read (b2) ra k, /k status qa qb qb rc qc qc qd qd nop nop nop write (b2) we de de df df dg dg dh dh wg write (b2) qa dq dq odt disabled qj qi ri qi read (b2) enabled disabled enabled odt on/off timing chart for r1qe series (ddr ii+, burst length=2, read latency=2.5 cycle) read (b2) read (b2) read (b2) rb rd wf wh rj read (b2) write (b2) write (b2) nop command read (b4) ra k, /k status qa qa qa rc qc qc qc qc nop nop nop write (b4) we de de de de dg dg dg dg wg write (b4) qa dq dq odt disabled qi qi ri qi read (b4) enabled disabled enabled odt on/off timing chart for r1qf series (ddr ii+, burst length=4, read latency=2.5 cycle) - read (b4) - - - - nop command read (b2) ra k, /k status qa qb qb rc qc qc qd qd nop nop write (b2) we de de df df dg dg dh dh wg write (b2) qa dq dq odt disabled qj qi ri qi read (b2) enabled disabled enabled odt on/off timing chart for r1ql series (ddr ii+, burst length=2, read latency=2.0 cycle) read (b2) read (b2) read (b2) rb rd wf wh rj read (b2) write (b2) write (b2) qj read (b2) rk qk qk nop command read (b4) ra k, /k status qa qa qa rc qc qc qc qc nop nop write (b4) we de de de de dg dg dg dg wg write (b4) qa dq dq odt disabled qi qi ri qi read (b4) enabled disabled enabled odt on/off timing chart for r1qm series (ddr ii+, burst length=4, read latency=2.0 cycle) - read (b4) - - - - qi read (b4) rk qk qk notes 1. odt on/off switching timings are edge aligned with cq or /cq. r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 --- k truth table operation k /r /w d or q write cycle: load address, input write data on two consecutive k and /k rising edges 9 h *7 l *8 data in input data d(a+0) d(a+1) d(a+2) d(a+3) input clock k(t+1) 9 /k(t+1) 9 k(t+2) 9 /k(t+2) 9 read cycle: load address, output read data on two consecutive c and /c rising edges 9 l *8 data out output data q(a+0) q(a+1) q(a+2) q(a+3) input clock for q rl *9 =1.5 /c(t+1) 9 c(t+2) 9 /c(t+2) 9 c(t+3) 9 rl=2.0 c(t+2) 9 /c(t+2) 9 c(t+3) 9 /c(t+3) 9 rl=2.5 /c(t+2) 9 c(t+3) 9 /c(t+3) 9 c(t+4) 9 nop (no operation) 9 hhd = or q = high-z standby (clock stopped) stopped previous state notes: 1. h: high level, l: low level, : dont care, 9 : rising edge. 2. data inputs are registered at k and /k rising edges. data outputs are delivered at c and /c rising edges, except if c and /c are high, then data outputs are delivered at k and /k rising edges. 3. /r and /w must meet setup/hold times around the rising edges (low to high) of k and are registered at the rising edge of k. 4. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 5. refer to state diagram and timing diagrams for clarification. 6. when clocks are stopped, the following cases are recommended; the case of k = low, /k = high, c = low and /c = high, or the case of k = high, /k = low, c = high and /c = low. this condition is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 7. if this signal was low to initiate the previous cycle, this signal becomes a dont care for this operation; however, it is strongly recommended that this signal be brought high, as shown in the truth table. 8. this signal was high on previous k clock rising edge. initiating consecutive read or write operations on consecutive k clock rising edges is not permitted. the device will ignore the second request. 9. rl = read latency (unit = cycle). r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 byte write truth table ( x 36 ) operation k /k /bw0 /bw1 /bw2 /bw3 write d0 to d35 9 -llll - 9 llll write d0 to d8 9 - lhhh - 9 lhhh write d9 to d17 9 -hlhh - 9 hlhh write d18 to d26 9 -hhlh - 9 hhlh write d27 to d35 9 -hhhl - 9 hhhl write nothing 9 - hhhh - 9 hhhh notes: 1. h: high level, l: low level, 9 : rising edge. 2. assumes a write cycle was initiated. /bwx can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. common byte write truth table ( x 18 ) operation k /k /bw0 /bw1 write d0 to d17 9 -l l - 9 ll write d0 to d8 9 -l h - 9 lh write d9 to d17 9 -h l - 9 hl write nothing 9 -h h - 9 hh notes: 1. h: high level, l: low level, 9 : rising edge. 2. assumes a write cycle was initiated. /bwx can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. byte write truth table ( x 9 ) operation k /k /bw write d0 to d8 9 -l - 9 l write nothing 9 -h - 9 h notes: 1. h: high level, l: low level, 9 : rising edge. 2. assumes a write cycle was initiated. /bwx can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. just reference except r1q2a**09 series r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 bus cycle state diagram notes: 1. the address is concatenated with two additional internal lsbs to facilitate burst operation. the address order is always fixed as: xxxxxx+0, xxxxxx+1, xxxxxx+2, xxxxxx+3. bus cycle is terminated at the end of this sequence (burst count = 4). 2. read and write state machines can be active simultaneously. read and write cannot be simultaneously initiated. read takes precedence. 3. state machine control timing sequence is controlled by k. read port nop r init = 0 read double r count = r count + 2 load new read address r count = 0 r init = 1 power up /r = h write port nop /w = h supply voltage provided supply voltage provided /r = l always /r = l & r count = 4 increment read address by two *1 r init = 0 always r count = 2 /r = h & r count = 4 write double w count = w count + 2 load new write address w count = 0 /w = l r init = 0 always /w = l & w count = 4 increment write address by two *1 always w count = 2 /w = h & w count = 4 --- r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 absolute maximum ratings parameter symbol rating unit notes input voltage on any ball v in ? 0.5 to v dd + 0.5 (2.5 v max.) v1, 4 input/output voltage v i/o ? 0.5 to v ddq + 0.5 (2.5 v max.) v1, 4 core supply voltage v dd ? 0.5 to 2.5 v 1, 4 output supply voltage v ddq ? 0.5 to v dd v1, 4 junction temperature tj +125 (max) c5 storage temperature t stg ? 55 to +125 c notes: 1. all voltage is referenced to v ss . 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted the operation conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. these cmos memory circuits have been designed to meet the dc and ac specifications shown in the tables after thermal equilibrium has been established. 4. the following supply voltage application sequence is recommended: v ss , v dd , v ddq , v ref then v in . remember, according to the absolute maximum ratings table, v ddq is not to exceed 2.5 v, whatever the instantaneous value of v ddq . 5. some method of cooling or airflow should be considered in the system. (especially for high frequency or odt parts) common recommended dc operating conditions parameter symbol min typ max unit notes power supply voltage -- core v dd 1.7 1.8 1.9 v 1 power supply voltage -- i/o v ddq 1.4 1.5 v dd v1, 2 input reference voltage -- i/o v ref 0.68 0.75 0.95 v 3 input high voltage v ih (dc) v ref + 0.1 ? v ddq + 0.3 v 1, 4, 5 input low voltage v il (dc) ? 0.3 ? v ref ? 0.1 v 1, 4, 5 notes: 1. at power-up, v dd and v ddq are assumed to be a linear ramp from 0v to v dd (min.) or v ddq (min.) within 200ms. during this time v ddq < v dd and v ih < v ddq . during normal operation, v ddq must not exceed v dd . 2. please pay attention to tj not to exceed the temperature shown in the absolute maximum ratings table due to current from v ddq . 3. peak to peak ac component superimposed on v ref may not exceed 5% of v ref . 4. these are dc test criteria. the ac v ih / v il levels are defined separately to measure timing parameters. 5. overshoot: v ih (ac) v ddq + 0.5 v for t t khkh /2 undershoot: v il (ac) ? 0.5 v for t t khkh /2 during normal operation, v ih(dc) must not exceed v ddq and v il(dc) must not be lower than v ss . r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 hins= 11111.1111 .1111.1111.1111-- - 00000.0000.0000.0000.0000--- 00000.0000.0000.0000.0000---072m dc characteristics (ta = 0 ~ +70 c @ r1q*a*****bb-** r ** series, ta = -40 ~ +85 c @ r1q*a*****bb-** i ** series) (v dd =1.8v 0.1v, v ddq =1.5v, v ref = 0.75v) operating supply current (write / read) symbol = i dd . unit = ma. see notes 1, 2 and 3 in the page after next. 533 500 450 400 375 333 333 300 250 200 1.875 2.00 2.22 2.50 2.66 3.00 3.00 3.30 4.00 5.00 yy -19-20-22-25-27-30-30-33-40-50 1 x 9 r1q 2 a72 09 a b v - yy 760 670 2x18r1q2a7218ab v - yy 890 780 3x36r1q2a7236ab v - yy 950 830 5x18r1q3a7218ab v - yy 880 820 730 6x36r1q3a7236ab v - yy 910 850 750 8x18r1q4a7218ab v - yy 750 700 630 9x36r1q4a7236ab v - yy 810 760 680 11 x18 r1q 5 a72 18 a b v - yy 660 630 590 12 x36 r1q 5 a72 36 a b v - yy 700 670 630 14 x18 r1q 6 a72 18 a b v - yy 750 700 630 15 x36 r1q 6 a72 36 a b v - yy 810 760 680 17 x18 r1q a a72 18 a b v - yy 1220 1160 1070 18 x36 r1q a a72 36 a b v - yy 1280 1220 1130 20 x18 r1q b a72 18 a b v - yy 1030 990 920 21 x36 r1q b a72 36 a b v - yy 1110 1060 990 23 x18 r1q c a72 18 a b v - yy 820 790 750 24 x36 r1q c a72 36 a b v - yy 880 850 800 26 x18 r1q d a72 18 a b v - yy 1220 1160 1070 27 x36 r1q d a72 36 a b v - yy 1280 1220 1130 29 x18 r1q e a72 18 a b v - yy 1030 990 920 30 x36 r1q e a72 36 a b v - yy 1110 1060 990 32 x18 r1q f a72 18 a b v - yy 820 790 750 33 x36 r1q f a72 36 a b v - yy 880 850 800 35 x18 r1q g a72 18 a b v - yy 1070 980 36 x36 r1q g a72 36 a b v - yy 1150 1060 38 x18 r1q h a72 18 a b v - yy 920 850 39 x36 r1q h a72 36 a b v - yy 990 910 41 x18 r1q j a72 18 a b v - yy 750 710 42 x36 r1q j a72 36 a b v - yy 800 760 44 x18 r1q k a72 18 a b v - yy 1070 980 45 x36 r1q k a72 36 a b v - yy 1150 1060 47 x18 r1q l a72 18 a b v - yy 920 850 48 x36 r1q l a72 36 a b v - yy 990 910 50 x18 r1q m a72 18 a b v - yy 750 710 51 x36 r1q m a72 36 a b v - yy 800 760 qdr ii+ / ddr ii+ qdr ii / ddr ii frequency (max) (mhz) cycle time (min) (ns) no yes no odt part number b2 1.5 no b2 b4 organi- zation 2.5 2.5 b4 b2 yes b4 qdrii ddrii sio b2 b2 ddrii+ ddrii b4 qdrii+ qdrii+ b4 2.0 ddrii+ b2 b4 2.0 b4 ddrii+ qdrii+ b4 ddrii+ b2 b4 qdrii+ b4 no product type burst length latency (cycle) notes: 1. " v " represents the package size . if " v " = " g " then size is 15 x 17 mm, and if " v " = " b " then 13 x 15 mm. 2. " yy " represents the speed bin . "r1qaa7236abb- 20 " can operate at 500 mhz(max) of frequency, for example. r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 hins= 11111.1111 .1111.1111.1111-- - 00000.0000.0000.0000.0000--- 00000.0000.0000.0000.0000---072m standby supply current (nop) symbol = i sb1 . unit = ma. see notes 2, 4 and 5 in the next page. 533 500 450 400 375 333 333 300 250 200 1.875 2.00 2.22 2.50 2.66 3.00 3.00 3.30 4.00 5.00 yy -19-20-22-25-27-30-30-33-40-50 1 x 9 r1q 2 a72 09 a b v - yy 570 510 2x18r1q2a7218ab v - yy 670 600 3x36r1q2a7236ab v - yy 710 630 5x18r1q3a7218ab v - yy 630 590 520 6x36r1q3a7236ab v - yy 650 610 540 8x18r1q4a7218ab v - yy 650 610 560 9x36r1q4a7236ab v - yy 710 670 610 11 x18 r1q 5 a72 18 a b v - yy 540 510 480 12 x36 r1q 5 a72 36 a b v - yy 570 540 500 14 x18 r1q 6 a72 18 a b v - yy 650 610 560 15 x36 r1q 6 a72 36 a b v - yy 710 670 610 17 x18 r1q a a72 18 a b v - yy 870 830 780 18 x36 r1q a a72 36 a b v - yy 910 870 810 20 x18 r1q b a72 18 a b v - yy 870 840 780 21 x36 r1q b a72 36 a b v - yy 960 920 860 23 x18 r1q c a72 18 a b v - yy 690 660 630 24 x36 r1q c a72 36 a b v - yy 730 710 670 26 x18 r1q d a72 18 a b v - yy 870 830 780 27 x36 r1q d a72 36 a b v - yy 910 870 810 29 x18 r1q e a72 18 a b v - yy 870 840 780 30 x36 r1q e a72 36 a b v - yy 960 920 860 32 x18 r1q f a72 18 a b v - yy 690 660 630 33 x36 r1q f a72 36 a b v - yy 730 710 670 35 x18 r1q g a72 18 a b v - yy 780 720 36 x36 r1q g a72 36 a b v - yy 830 770 38 x18 r1q h a72 18 a b v - yy 780 720 39 x36 r1q h a72 36 a b v - yy 860 790 41 x18 r1q j a72 18 a b v - yy 630 590 42 x36 r1q j a72 36 a b v - yy 670 630 44 x18 r1q k a72 18 a b v - yy 780 720 45 x36 r1q k a72 36 a b v - yy 830 770 47 x18 r1q l a72 18 a b v - yy 780 720 48 x36 r1q l a72 36 a b v - yy 860 790 50 x18 r1q m a72 18 a b v - yy 630 590 51 x36 r1q m a72 36 a b v - yy 670 630 qdr ii+ / ddr ii+ qdr ii / ddr ii frequency (max) (mhz) cycle time (min) (ns) no yes no odt part number b2 1.5 no b2 b4 organi- zation 2.5 2.5 b4 b2 yes b4 qdrii ddrii sio b2 b2 ddrii+ ddrii b4 qdrii+ qdrii+ b4 2.0 ddrii+ b2 b4 2.0 b4 ddrii+ qdrii+ b4 ddrii+ b2 b4 qdrii+ b4 no product type burst length latency (cycle) notes: 1. " v " represents the package size . if " v " = " g " then size is 15 x 17 mm, and if " v " = " b " then 13 x 15 mm. 2. " yy " represents the speed bin . "r1qaa7236abb- 20 " can operate at 500 mhz(max) of frequency, for example. r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 common leakage currents & output voltage parameter symbol min max unit test condition notes input leakage current i li ? 22 a10 output leakage current i lo ? 55 a11 output high voltage v oh (low) v ddq ? 0.2 v ddq v|i oh | 0.1 ma 8, 9 v oh v ddq /2 ? 0.12 v ddq /2 + 0.12 v note 6 8, 9 output low voltage v ol (low) v ss 0.2 v i ol 0.1 ma 8, 9 v ol v ddq /2 ? 0.12 v ddq /2 + 0.12 v note 7 8, 9 notes: 1. all inputs (except zq, v ref ) are held at either v ih or v il . 2. i out = 0 ma. v dd = v dd max, t khkh = t khkh min. 3. operating supply currents (i dd ) are measured at 100% bus utilization. i dd of qdr family is current of device with 100% write and 100% read cycle. i dd of ddr family is current of device with 100% write cycle (if i dd (write) > i dd (read)) or 100% read cycle (if i dd (write) < i dd (read)). 4. all address / data inputs are static at either v in > v ih or v in < v il . 5. reference value. (condition = nop currents are valid when entering nop after all pending read and write cycles are completed. ) 6. outputs are impedance-controlled. |i oh | = (v ddq /2)/(rq/5) for values of 175 ? rq 350 . 7. outputs are impedance-controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ? rq 350 . 8. ac load current is higher than the shown dc values. ac i/o curves are available upon request. 9. hstl outputs meet jedec hstl class i and class ii standards. 10. 0 v in v ddq for all input balls (except v ref , zq, tck, tms, tdi ball). if r1qd, r1qe, r1qf, r1qk, r1ql, r1qm, r1qp series, balls with odt do not follow this spec. 11. 0 v out v ddq (except tdo ball), output disabled. r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 hins= 11111.1111 .1111.1111.1111-- -11111.1111 .1111.1111.1111 --- 00000.0000.0000.0000.0000 ---72m_36m ac test conditions input waveform (rise/fall time 1.25v 0.25v 0.75v 0.75v test points output waveform v ddq /2 test points v ddq /2 capacitance (ta = +25 c, frequency = 1.0mhz, v dd =1.8v, v ddq =1.5v) parameter symbol min typ max unit test condition notes input capacitance (sa, /r, /w, /bw, d (separate) ) c in ? 45pf v in = 0 v 1, 2 clock input capacitance (k, /k, c, /c) c clk ? 45pf v clk = 0 v 1, 2 output capacitance (q (separate) , dq (common) , cq, /cq) c i/o ? 56pf v i/o = 0 v 1, 2 notes: 1. these parameters are sampled and not 100% tested. 2. except jtag (tck, tms, tdi, tdo) pins. thermal resistance parameter symbol airflow typ unit test condition notes junction to ambient ja 1 m/s 11.0 c/w eia/jedec jesd51 1 junction to case jc -4.4 notes: 1. these parameters are calculated under the condition. these are reference values. 2. tj = ta + ja ? pd tj = tc + jc ? pd where tj : junction temperature when the device has achieved a steady-state after application of pd ( r c) ta : ambient temperature ( r c) tc : temperature of external surface of the package or case ( r c) ja : thermal resistance from junction-to-ambient ( r c/w) jc : thermal resistance from junction-to-case (package) ( r c/w) pd : power dissipation that produced change in junction temperature (w) (cf.jesd51-2a) r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 common ac operating conditions parameter symbol min typ max unit notes input high voltage v ih (ac) v ref + 0.2 ?? v 1, 2, 3, 4 input low voltage v il (ac) ?? v ref C 0.2 v 1, 2, 3, 4 notes: 1. all voltages referenced to v ss (gnd). during normal operation, v ddq must not exceed v dd . 2. these conditions are for ac functions only, not for ac parameter test. 3. overshoot: v ih (ac) v ddq + 0.5 v for t t khkh /2 undershoot: v il (ac) ? 0.5 v for t t khkh /2 control input signals may not have pulse widths less than t khkl (min) or operate at cycle rates less than t khkh (min). 4. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through the target ac level, v il (ac) or v ih (ac) . b. reach at least the target ac level. c. after the ac target level is reached, continue to maintain at least the target dc level, v il (dc) or v ih (dc) . output load conditions output load and voltage conditions 50 zq q v ref 250 z 0 = 50 sram v ddq / 2 = 0.75v v ddq / 2 = 0.75v v dd v ddq v ss 1.8v 0.1v 1.5v r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 hins=00000.0000.0000.0111.0111 -- - 00000.0000.0000.0111.0111- -- 00000.0000.0000.0000.0000 ---rl=2.0 ac characteristics ( read latency = 2.0 cycle ) (ta = 0 ~ +70 c @ r1q*a*****bb-** r ** series) (ta = -40 ~ +85 c @ r1q*a*****bb-** i ** series) (v dd =1.8v 0.1v, v ddq =1.5v, v ref = 0.75v) parameter symbol -19 -20 -22 -25 -27 -30 unit notes min max min max min max min max min max min max clock average clock cycle time (k, /k) t khkh 1.875 4.00 2.00 4.00 2.22 4.00 2.50 4.00 2.66 4.00 3.00 4.00 ns clock high time (k, /k) t khkl 0.40 ? 0.40 ? 0.40 ? 0.40 ? 0.40 ? 0.40 ? cy- cle clock low time (k, /k) t klkh 0.40 ? 0.40 ? 0.40 ? 0.40 ? 0.40 ? 0.40 ? cy- cle clock to /clock (k to /k) t kh/kh 0.425 ? 0.425 ? 0.425 ? 0.425 ? 0.425 ? 0.425 ? cy- cle /clock to clock (/k to k) t /khkh 0.425 ? 0.425 ? 0.425 ? 0.425 ? 0.425 ? 0.425 ? cy- cle ?? ? ? ? ? ? ? ? ? ? ? ? ? ?? dll/pll timing clock phase jitter (k, /k) t kc var ? 0.15 ? 0.15 ? 0.15 ? 0.20 ? 0.20 ? 0.20 ns 3 lock time (k) t kc lock 20 ? 20 ? 20 ? 20 ? 20 ? 20 ? us 2 k static to dll/pll reset t kc reset 30 ? 30 ? 30 ? 30 ? 30 ? 30 ? ns 7 output times k, /k high to output valid t chqv ? 0.55 ? 0.55 ? 0.55 ? 0.55 ? 0.55 ? 0.55 ns k, /k high to output hold t chqx ? 0.35 ? ? 0.35 ? ? 0.35 ? ? 0.35 ? ? 0.35 ? ? 0.35 ? ns k, /k high to echo clock valid t chcqv ? 0.55 ? 0.55 ? 0.55 ? 0.55 ? 0.55 ? 0.55 ns k, /k high to echo clock hold t chcqx ? 0.35 ? ? 0.35 ? ? 0.35 ? ? 0.35 ? ? 0.35 ? ? 0.35 ? ns cq, /cq high to output valid t cqhqv ? 0.15 ? 0.15 ? 0.15 ? 0.20 ? 0.20 ? 0.20 ns 4, 7 cq, /cq high to output hold t cqhqx ? 0.15 ? ? 0.15 ? ? 0.15 ? ? 0.20 ? ? 0.20 ? ? 0.20 ? ns 4, 7 k, /k high to output high-z t chqz ? 0.55 ? 0.55 ? 0.55 ? 0.55 ? 0.55 ? 0.55 ns 5, 6 k, /k high to output low-z t chqx1 ? 0.35 ? ? 0.35 ? ? 0.35 ? ? 0.35 ? ? 0.35 ? ? 0.35 ? ns 5 /cq high to qvld valid t qvld ? 0.15 0.15 ? 0.15 0.15 ? 0.15 0.15 ? 0.20 0.20 ? 0.20 0.20 ? 0.20 0.20 ns 7 r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 hins=00000.0000.0000.0111.0111 -- - 00000.0000.0000.0111.0111 --- 00000.0000.0000.0000.0000 ---rl=2.0 parameter symbol -19 -20 -22 -25 -27 -30 unit notes min max min max min max min max min max min max setup times address valid to k rising edge t avkh (qdrii+ b2) ? ? ? ? ? ? ? ? ? ? ? ? ns 1, 8 t avkh (qdrii+ b4 & ddrii+) 0.30 ? 0.33 ? 0.40 ? 0.40 ? 0.40 ? 0.40 ? control inputs valid to k rising edge t ivkh (qdrii+ b2) ? ? ? ? ? ? ? ? ? ? ? ? ns 1, 8 t ivkh (qdrii+ b4 & ddrii+) 0.30 ? 0.33 ? 0.40 ? 0.40 ? 0.40 ? 0.40 ? data-in valid to k, /k rising edge t dvkh 0.20 ? 0.22 ? 0.25 ? 0.28 ? 0.28 ? 0.28 ? ns 1, 9 hold times k rising edge to address hold t khax (qdrii+ b2) ? ? ? ? ? ? ? ? ? ? ? ? ns 1, 8 t khax (qdrii+ b4 & ddrii+) 0.30 ? 0.33 ? 0.40 ? 0.40 ? 0.40 ? 0.40 ? k rising edge to control inputs hold t khix (qdrii+ b2) ? ? ? ? ? ? ? ? ? ? ? ? ns 1, 8 t khix (qdrii+ b4 & ddrii+) 0.30 ? 0.33 ? 0.40 ? 0.40 ? 0.40 ? 0.40 ? k, /k rising edge to data-in hold t khdx 0.20 ? 0.22 ? 0.25 ? 0.28 ? 0.28 ? 0.28 ? ns 1, 9 notes: 1. this is a synchronous device. all addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 2. v dd and v ddq slew rate must be less than 0.1 v dc per 50 ns for dll/pll lock retention. dll/pll lock time begins once v dd , v ddq and input clock are stable. it is recommended that the device is kept inactive during these cycles. this specification meets the qdr common spec. of 20 us. 3. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. echo clock is very tightly controlled to data valid / data hold. by design, there is a 0.1 ns variation from echo clock to data. the datasheet parameters reflect tester guardbands and test setup variations. 5. transitions are measured 100 mv from steady-state voltage. 6. at any given voltage and temperature t chqz is less than t chqx1 and t chqv . 7. these parameters are sampled. 8. t avkh , t ivkh , t khax , t khix spec is determined by the actual frequency regardless of part number (marking name). the following is the spec for the actual frequency. 0.30 ns for ? 533mhz & >500mhz 0.33 ns for ? 500mhz & >450mhz 0.40 ns for ? 450mhz & ? 250mhz 9. t dvkh , t khdx spec is determined by the actual frequency regardless of part number (marking name). the following is the spec for the actual frequency. 0.20 ns for ? 533mhz & >500mhz 0.22 ns for ? 500mhz & >450mhz 0.25 ns for ? 450mhz & >400mhz 0.28 ns for ? 400mhz & ? 250mhz remarks: 1. test conditions as specified with the output loading as shown in ac test conditions unless otherwise noted. 2. control input signals may not be operated with pulse widths less than t khkl (min). 3. v ddq is +1.5 v dc. v ref is +0.75 v dc. 4. control signals are /r, /w (qdr series), /ld, r-/w (ddr series), /bw, /bw0, /bw1, /bw2 and /bw3. setup and hold times of /bwx signals must be the same as those of data-in signals. r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 hins=00000.0000.0000.0100.0100 -- - 00000.0000.0000.0100.0100 ---00000.0000.0000.0100.0100--- r1qa_rl=2.0 r tqvld -tqvld tqvld -tqvld q00 qx3 q01 q02 q03 q20 q21 q22 q23 qx2 qx1 tchqv -tchqx tchqv -tchqx tcqhqv -tcqhqx -tchqx1 tchqz tchcqv -tchcqx tchcqv -tchcqx timing waveforms read and write timing (qdrii+, b4, read latency = 2.0 cycle) k a0 d10 a1 a2 a3 d11 d12 d13 d30 d31 d32 d33 nop read write read write nop nop nop tkhix tivkh tkhix tivkh tkhax tavkh tkhdx tdvkh tkhdx tdvkh /k /r /w address data in tkhkh tkhkl tklkh tkh/kh t/khkh data out cq /cq notes: 1. q00 refers to output from address a0+0. q01 refers to output from the next internal burst address following a0, i.e., a0+1. 2. outputs are disabled (high-z) n clock cycle after the last read cycle. here, n = read latency + burst length 0.5. 3. in this example, if address a2 = a1, then data q20 = d10, q21 = d11. write data is forwarded immediately as read results. 4. to control read and write operations, /bw signals must operate at the same timing as data-in signals. 1 2 3 4 5 6 7 8 9 qvld r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 jtag specification these products support a limited set of jtag functions as in ieee standard 1149.1. disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, tck must be tied to v ss to preclude mid level inputs. tdi and tms are internally pulled up and may be unconnected, or may be connected to vdd through a pull up resistor. tdo should be left unconnected. test access port (tap) pins symbol i/o pin assignments description notes tck 2r test clock input. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms 10r test mode select. this is the command input for the tap controller state machine. tdi 11r test data input. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction. tdo 1r test data output. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. notes: the device does not have trst (tap reset). the test-logic reset state is entered while tms is held high for five rising edges of tck. the tap controller state is also reset on sram power-up. common r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 tap dc operating characteristics (ta = 0 ~ +70 c @ r1q*a*****bb-** r ** series) (ta = -40 ~ +85 c @ r1q*a*****bb-** i ** series) (v dd =1.8v 0.1v) parameter symbol min typ max unit notes input high voltage v ih +1.3 ? v dd + 0.3 v input low voltage v il ? 0.3 ?+ 0.5 v input leakage current i li ? 5.0 ?+ 5.0 a0 v v in v dd output leakage current i lo ? 5.0 ?+ 5.0 a 0 v v in v dd , output disabled output low voltage v ol1 ?? 0.2 v i olc = 100 a v ol2 ?? 0.4 v i olt = 2 ma output high voltage v oh1 1.6 ?? v|i ohc | = 100 a v oh2 1.4 ?? v|i oht | = 2 ma notes: 1. all voltages referenced to v ss (gnd). 2. at power-up, v dd and v ddq are assumed to be a linear ramp from 0v to v dd (min.) or v ddq (min.) within 200ms. during this time v ddq < v dd and v ih < v ddq . during normal operation, v ddq must not exceed v dd . common r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 tap ac test conditions parameter symbol conditions unit notes input timing measurement reference levels v ref 0.9 v input pulse levels v il , v ih 0 to 1.8 v input rise/fall time tr, tf 1.0 ns output timing measurement reference levels 0.9 v test load termination supply voltage (v tt ) 0.9 v output load see figures common external load at test 50 input waveform 0v 0.9v 0.9v test points output waveform 0.9v test points 0.9v output load condition r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 tap ac operating characteristics (ta = 0 ~ +70 c @ r1q*a*****bb-** r ** series) (ta = -40 ~ +85 c @ r1q*a*****bb-** i ** series) (v dd =1.8v 0.1v) parameter symbol min typ max unit notes test clock (tck) cycle time t thth 50 ?? ns tck high pulse width t thtl 20 ?? ns tck low pulse width t tlth 20 ?? ns test mode select (tms) setup t mvth 5 ?? ns tms hold t thmx 5 ?? ns capture setup t cs 5 ?? ns 1 capture hold t ch 5 ?? ns 1 tdi valid to tck high t dvth 5 ?? ns tck high to tdi invalid t thdx 5 ?? ns tck low to tdo unknown t tlqx 0 ?? ns tck low to tdo valid t tlqv ?? 10 ns notes: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to assure pad data capture. common r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 test access port registers register name length symbol notes instruction register 3 bits ir [2:0] bypass register 1 bit bp id register 32 bits id [31:0] boundary scan register 109 bits bs [109:1] tap controller timing diagram tck tdi tms tdo pi (sram) tthtl tthth ttlth tmvth tthmx tdvth tthdx tcs tch ttlqv ttlqx common r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 tap controller instruction set ir2 ir1 ir0 instruction description notes 0 0 0 extest the extest instruction allows circuitry external to the component package to be tested. boundary scan register cells at output balls are used to apply test vectors, while those at input balls capture test results. typically, the first test vector to be applied using the extest instruction will be shifted into the boundary scan register using the preload instruction. thus, during the update-ir state of extest, the output driver is turned on and the preload data is driven onto the output balls. 1, 2, 3, 5 0 0 1 idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo balls in shift- dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. 0 1 0 sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (high-z), moving the tap controller into the capture-dr state loads the data in the rams input into the boundary scan register, and the boundary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. 3, 4, 5 0 1 1 reserved the reserved instructions are not implemented but are reserved for future use. do not use these instructions. 100 sample (/preload) when the sample instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. because the ram clock(s) are independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable input will not harm the device, repeatable results cannot be expected. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo balls. 3, 5 1 0 1 reserved - 1 1 0 reserved - 1 1 1 bypass the bypass instruction is loaded in the instruction register when the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing of other dev ices in the scan path. notes: 1. data in output register is not guaranteed if extest instruction is loaded. 2. after performing extest, power-up conditions are required in order to return part to normal operation. 3. ram input signals must be stabilized for long enough to meet the taps input data capture setup plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. 4. clock recovery initialization cycles are required after boundary scan. 5. for r1qd, r1qe, r1qf, r1qk, r1ql, r1qm, r1qp series, odt is disabled in extest, sample-z or sample mode. common r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 72--- boundary scan order bit # ball id signal names bit # ball id signal names x9 x18 x36 x9 x18 x36 16r /c or nc or odt /c or nc or odt /c or nc or odt 36 10e d3 d6 d6 26p c or qvld c or qvld c or qvld 37 10d nc nc d15 36nsasasa389encncq15 47psasasa3910cncq7q7 5 7n sa sa sa 40 11d nc d7 d7 67rsasasa419cncncd16 78rsasasa429dncncq16 8 8p sa sa sa 43 11b q4 q8 q8 9 9r sa sa sa 44 11c d4 d8 d8 1011pq0q0q0459bncncd17 11 10p d0 d0 d0 46 10b nc nc q17 12 10n nc nc d9 47 11a cq cq cq 13 9p nc nc q9 48 10a sa sa nc 14 10m nc q1 q1 49 9a sa sa sa 1511nncd1d1508bsasasa 16 9m nc nc d10 51 7c sa sa sa 17 9n nc nc q10 52 6c nc nc nc 1811lq1q2q2538a/r /r /r 1911md1d2d2547ancnc/bw1 20 9l nc nc d11 55 7b /bw /bw0 /bw0 21 10l nc nc q11 56 6b k k k 2211kncq3q3576a/k/k/k 23 10k nc d3 d3 58 5b nc nc /bw3 24 9j nc nc d12 59 5a nc /bw1 /bw2 25 9k nc nc q12 60 4a /w /w /w 26 10j q2 q4 q4 61 5c sa sa sa 2711jd2d4d4624bsasasa 2811hzqzqzq633asasasa 29 10g nc nc d13 64 2a sa nc nc 30 9g nc nc q13 65 1a /cq /cq /cq 3111fncq5q5662bncq9q18 3211gncd5d5673bncd9d18 33 9f nc nc d14 68 1c nc nc d27 34 10f nc nc q14 69 1b nc nc q27 3511eq3q6q6703dncq10q19 r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 --- boundary scan order bit # ball id signal names bit # ball id signal names x9 x18 x36 x9 x18 x36 71 3c nc d10 d19 91 2l q7 q15 q24 72 1d nc nc d28 92 3l d7 d15 d24 73 2c nc nc q28 93 1m nc nc d33 74 3e q5 q11 q20 94 1l nc nc q33 75 2d d5 d11 d20 95 3n nc q16 q25 76 2e nc nc d29 96 3m nc d16 d25 77 1e nc nc q29 97 1n nc nc d34 78 2f nc q12 q21 98 2m nc nc q34 79 3f nc d12 d21 99 3p q8 q17 q26 80 1g nc nc d30 100 2n d8 d17 d26 81 1f nc nc q30 101 2p nc nc d35 82 3g q6 q13 q22 102 1p nc nc q35 83 2g d6 d13 d22 103 3r sa sa sa 84 1h /doff /doff /doff 104 4r sa sa sa 85 1j nc nc d31 105 4p sa sa sa 86 2j nc nc q31 106 5p sa sa sa 87 3k nc q14 q23 107 5n sa sa sa 88 3j nc d14 d23 108 5r sa sa sa 89 2k nc nc d32 109 ? inter- nal inter- nal inter- nal 90 1k nc nc q32 ?? ? ? ? notes: in boundary scan mode, 1. clock balls (k, /k, c, /c) are referenced to each other and must be at opposite logic levels for reliable operation. 2. cq and /cq data are synchronized to the respective c and /c (except extest, sample-z). 3. if c and /c tied high, cq is generated with respect to k and /cq is generated with respect to /k (except extest, sample-z). r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 tap controller state diagram notes: the value adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck. no matter what the original state of the controller, it will enter test-logic-reset when tms is held high for at least five rising edges of tck. select ir scan capture ir shift ir exit1 ir pause ir exit2 ir update ir 0 0 1 0 1 1 0 1 0 0 1 select dr scan capture dr shift dr exit1 dr pause dr exit2 dr update dr 0 0 1 0 1 1 0 1 0 0 1 run test/idle 0 10 1 test logic reset 1 1 0 0 11 common id register b? b? # 313029282726252423222120191817161514131211109876543210 symbol rrr0cmmmaww01qqqbos0010001000111 rrr q 000 0 001 1 010 q 011 0 1 cq 00 11 mmm b 010 0 011 1 101 o 110 0 a1 0s 10 ww 1 00 10 11 :: density = 72mb density = 36mb latency=1.5 (@ii), latency=2.0 (@ii+) latency=2.5 (@ii+) burst length = 2 word burst revis on 0 ii (q dr-ii, ddr-ii) revison 1 revison 2 revison 3 start bit (0) g - revision number (31 :29) type number (28 : 12) x36 36m&72m w/o odt, 144m,288m 36m&72m w/ odt 144m&288m w/o odt, 36m,72m 144m&288m w/ odt burst length = 4 word burst density = 144mb density = 288mb common i/o separate i/o vendor jedec code x18 x9 (11 : 1) ii+ (q dr-ii+, ddr-ii+) ddr qdr with odt without odt r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 package dimensions and marking information both pb parts and pb-free parts are available. hins= 11111.1111 .1111.1111.1111-- - 11111.1111 .1111.1111.1111 --- 00000.0000.0000.0000.0000 ---72m_36m -ys - ?x(m) s ab top view side view bottom view marking information 1st row : vender name (r enesas ) 2nd row: part number 3rd row : y : year code ww : week code xxxx : renesas internal use 4th row : country name (japan) + "none" --- pb -free parts + "pb-f" --- pb-free parts s a1 a z e z d abcdefghjklmnpr 1234567891011 [e] [e] ?b index mark a d index mark (laser mark) b e r1qga7218abb-25r ywwxxxx japan pb-f this part number or mark is just one example. jeita package code renesas code previous code mass (typ.) p-lbga165-13x15-1.00 plbg0165fe-a 165fhg 0.5g reference symbol dimension in mm min nom max d 12.9 13.0 13.1 e 14.9 15.0 15.1 a - - 1.4 a1 0.31 0.36 0.41 [e] - 1.0 - b 0.45 0.5 0.6 x - - 0.2 y - - 0.15 z d - 2.5 - z e - 1.5 - r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 hins=00000. 0100.0100.0100.0100 -- - 00000.0000.0000.0000.0000--- 00000.0000.0000.0000.0000---72m_qdrii+_b4 appendix example of dc/ac characteristics data parts number : r1qaa7236rbg-19r idd (operating supply current) - tkhkh (ta=70 degc) tnn vnn onnn opnn ornn ols pln pls qln ?ifif>f??g g??>f?_g qnca t??[olut t??[olvt t??[olwt k??????>?? tkhkh (clock cycle time) shmoo (ta=70 degc) 6+/' 05 05 05 05 05 05 8qnvcig 8 2222222222222222222222222 22222222222222222222 8 2222222222222222222222222 22222222222222222222 2 2cuu 8 222222 2 222 2 222 2 222 2 222 2 222 2 222 2 2 22222222222222222222 52'% 8 222222 2 222 2 222 2 222 2 222 2 222 2 222 2 2 22222222222222222222 8 222222 2 222 2 222 2 222 2 222 2 222 2 222 2 2 22222222222222222222 8 222222 2 222 2 222 2 222 2 222 2 222 2 222 2 2 22222222222222222222 8 222222 2 222 2 222 2 222 2 222 2 222 2 222 2 2 22222222222222222222 8 2222222222222222222222222 22222222222222222222 8 2222222222222222222222222 22222222222222222222 05 05 05 05 05 05 tkhkh tchqv (k, /k high to output valid) shmoo (ta=70 degc) 6+/' 25 25 25 25 25 25 8qnvcig 8 2 222222222222222222 8 2222222222222222222 2 2cu u 8 2 222222222222 2 222 2 2 2 2 52'% 8 2222222222222 2 222 2 222 8 2222222222222 2 222 2 222 8 2222222222222 2 222 2 222 8 2222222222222 2 222 2 222 8 2222222222222222222 8 2222222222222222222 25 25 25 25 25 25 tchqv vdd vdd r10ds0172ej0011
r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 hins= 11111.1111 .1111.1111.1111-- - 11111.1111 .1111.1111.1111 --- 00000.0000.0000.0000.0000 ---72m_36m revision history rev. date description revision history (1) 4gx &cvg %qoogpv 4gxc +pkvkcnkuuwg 4gxd %qttgevgfv[rqukp&%%jctcevgtkuvkeu81* 81.8&&3dd 4gxe #ffgf5rggf$kp6cdng #ffgf1&6vkokpiejctvvq3&4++ cpf&&4++ ugtkgu %qttgevgfv[rqukp)gpgtcn&guetkrvkqp1&6rkp3?3p& ?&p 7rfcvgf4geqoogpfgf&%1rgtcvkpi%qpfkvkqpu8tgh?8 ? 8
++ ugtkgu #ffgfeqoogpvvq6jgtocn4gukuvcpegugevkqp6jgugctgtghgt gpegxcnwgu 4gxg #ffgf)gpgtcvkqp0wodgt6cdng %jcpigf/ctmkpi0cogkp2ctv0wodgt&ghkpkvkqp6cdng #ffgfoctmkpikphqtocvkqpvq2cemcig&kogpukqp+phqtocvkqpu gevkqp %qttgevgf1&61p1hhvkokpikp1&6rkpvcdng 7rfcvgfokpkowohtgswgpe[qh3&4++ cpf&&4++ ugtkgu %jcpigfrkppcogkp2kp#ttcpigogpvqh&&4++ ugtkgu5#5# 0% #ffgfvjgtqyvq-6twvj6cdng4.cpf4. 7rfcvgf5'672e[engu++ ugtkgu&..nqemvkogwu e[eng #ffgfeqoogpvvq1&6qpqhh6kokpi%jctvugevkqp1&6qpqhh uykvejkpi vkokpiuctggfigcnkipgfykvj%3qt%3 7rfcvgf6jgtocn4gukuvcpeg 4gxj #ffgfurggfdkpvq3&4++$zzu gtkgu 7rfcvgf2cemcig&kogpukqpu/cuui#
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r1gaa72 / r1qka72 series rev. 0.11 : 2013.01.15 hins= 11111.1111 .1111.1111.1111-- - 11111.1111 .1111.1111.1111 --- 00000.0000.0000.0000.0000 ---72m_36m revision history (2) r10ds0172ej0011
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